N-type metal-oxide-silicon (NMOS) transistors such as transistor 100 of FIG. 1 are a frequent choice for ESD protection circuits for integrated circuits. Transistor 100 comprises N-type source and drain regions 110, 120 in a P-type well 130 in substrate 140, an insulating layer 150 on the substrate and a gate 160 on the insulating layer between the source and drain regions. Sidewall spacers 162 are located on each side of gate 160; and lightly doped drain (LDD) regions 170, 180 extend part way under the gate from the source and drain regions. Transistor 100 operates to provide ESD protection by triggering a parasitic lateral bipolar transistor 190 inherent in the MOS structure where the source and drain regions 110, 120 of the MOS transistor constitute the emitter and collector of the lateral bipolar transistor and the well 130 constitutes the base. See, for example, A. Amerasekera et al., ESD in Silicon Integrated Circuits, pp. 81-95 (2d Ed., Wiley, 2002).
In an integrated circuit (IC), a typical implementation of a MOS transistor is as a multi-fingered gate structure 200 such as that shown in a top view in FIG. 2A and in cross-section in FIG. 2B taken along line B-B of FIG. 2A. For convenience, only four of the fingers of the device of FIG. 2A have been shown in FIG. 2B. Structure 200 comprises N-type source and drain regions 210, 220 in a P-well 230 in substrate 240, an insulating layer 250 on the substrate and a multi-fingered gate 260 on the insulating layer. LDD regions 270, 280 extend part way under each gate finger. Structure 200 further includes a P-well tap 290 on the periphery of the structure and a shallow trench isolation region 252 between the source and drain regions and the P-well tap. The source regions 210 are connected together by a connector 215 that is typically formed in a metallization layer on the IC; the drain regions 220 are connected together by a connector 225 also formed in a metallization layer on the IC; and the gate fingers are connected together by a connector 265 also formed in a metallization layer on the IC. As a result, the source regions, drain regions and gate fingers are connected in parallel. The dimension L is the gate length; the dimension W is the width of a gate finger. Since the source regions, drain regions and fingers are connected in parallel, the total gate width of the transistor is the product of W and the number of fingers, or 8 W for the device shown in FIG. 2A.
One type of circuit in which the NMOS transistor is used for ESD protection is a circuit such as circuit 300 of FIG. 3 that is designed for use with multiple I/O standards. Different I/O standards have been developed to interface with memories, microprocessors, backplanes and peripheral devices that use different power supply voltages, signaling protocols or terminations.
Examples of the different I/O standards include:
                LVTTL which is defined by JEDEC Standard JESD 8-A, Interface Standard for Nominal 3.0 V/3.3V Supply Digital Integrated Circuits,        LVCMOS which is defined by JEDEC Standard JESD 8-A, Interface Standard for Nominal 3.0V/3.3V Supply Digital Integrated Circuits;        2.5V which is documented by JEDEC Standard JESD 8-5, 2.5V±0.2V (Normal Range) and 1.7V to 2.7V (Wide Range) Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit;        1.8V which is documented by JEDEC Standard JESD 8-7, 1.8V±0.15 (Normal Range) and 1.2V to 1.95V (Wide Range) Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit;        3.3V PCI which is defined in PCI Local Bus Specification Revision 2.2;        LVDS which is defined in IEEE 1596.3 SCI-LVDS and ANSI/TIA/EIA-644;        HSTL Class I, which is specified by JEDEC Standard JESD 8-6, High-Speed Transceiver Logic (HSTL);        SSTL-2, Class I & II, which is specified by JEDEC Standard JESD 8-9, Stub-Series Terminated Logic for 2.5 Volts (SSTL-2);        SSTL 3 Class I & II, which is specified by JEDEC Standard JESD 8-8, Stub-Series Terminated Logic for 3.3 Volts (SSTL-3);        CCT which is specified by JEDEC Standard JESD 8-4, Center-Tap-Terminated (CTT) Low-Level, High-Speed Interface Standard for Digital Integrated Circuits.        
Circuit 300 comprises a plurality of input circuits 310A, 310B, . . . 310N connected in parallel to a power supply bus 370, an input/output (I/O) bus 380 and ground 390. Each input circuit is used with a different I/O standard. Each input circuit comprises a pair of inverters 320, 322, an NMOS transistor 350 and a PMOS transistor 360. NMOS transistor 350 is structurally similar to transistor 200 of FIGS. 2A and 2B and comprises N-type source 351 and drain regions 352 in a P-type well and a gate 356. Source 351 is connected to ground 390 and drain 352 is connected to I/O bus 380. PMOS transistor 360 is structurally similar to transistor 200 but has opposite conductivity type. Thus, in addition to a gate 366, it has P-type source and drain regions 361, 362 in an N-type well. Source 361 is connected to the power supply bus 370 and drain 362 is connected to I/O bus 380. While each of the input circuits 310A, 310B, . . . 310N is depicted in FIG. 3 as having the same topology, a major difference among the input circuits is in the size of transistors 350 and 360 which varies from one circuit to another. Since it is advantageous to use the same gate length in all the transistors in the integrated circuit, this variation in size is achieved by varying the gate width of the transistors in the different input circuits.
Each of inverters 320, 322 typically comprises an NMOS transistor 330 and a PMOS transistor 340 connected in series between power supply bus 370 and ground 390. For convenience, only transistors 330 and 340 of inverter 320 are shown in FIG. 3. The transistors of inverter 322 will be understood to be similar. NMOS transistor 330 comprises a source 331, a drain 332 and a gate 336. Similarly, PMOS transistor 340 comprises a source 341, a drain 342 and a gate 346. Source 331 is connected to ground 390 and drain 332 is connected to an output node 339. Source 341 is connected to power supply bus 370 and drain 342 is connected to output node 339. Gates 336 and 346 are connected to an input node 338. Output node 339 is connected to gate 356 of NMOS transistor 350. Similarly, inverter 322 has an input node 348 connected to the gates of its PMOS and NMOS transistors and an output node 349 connected to gate 366 of PMOS transistor 360. The size of the transistors in inverters 320, 322 is typically the same in each input circuit.
As noted above, to accommodate different I/O standards, the size of the NMOS and PMOS transistors 350, 360 in input circuits 310A, 310B, . . . 310N is varied. This variation in size is considerable; and in some commercially available multiple I/O standards circuits the NMOS transistor in one input circuit may have a gate width that is as large as the sum of the gate widths of the NMOS transistors in all the other input circuits. When the NMOS transistors 350 are used for ESD protection, their variation in size ordinarily results in the largest NMOS transistor turning on before the other transistors. As a result, the ESD pulse is discharged through that transistor alone. This has the effect of limiting the ESD protection capabilities of the circuit to what can be discharged through the one largest transistor.
Additional limitations on ESD protection capabilities arise from the structure of the transistor itself. As is apparent from FIGS. 2A and 2B, there is considerable variation in distance between the P-well tap 290 and the different gate fingers of the multi-fingered transistor. As a result, the electric potential of the well under the different gate fingers varies from one finger to another. Since the triggering of the parasitic bipolar transistor depends on forward biasing the P-N junction between the P-type well and the N-type source region, the potential at some portions of the multi-fingered structure may not be enough to trigger the parasitic transistor in those portions. As a result, triggering of the transistor tends to be non-uniform with the result that the transistor is not able to discharge as large an ESD pulse as it could if triggering were substantially uniform across the entire multi-fingered structure. Conventional efforts to increase the potential under the gate fingers usually involve increasing the distance between these regions and the P-well tap. The penalty for this, however, is an increase in the size of the transistor.